In February 2019, I visited the Embedded World Fair in Nuremberg, Germany. Western Digital said at the show that its products already use RISC-V architecture processors, shipping more than 1 billion RISC-V chips a year and expected to double that in the future. The RISC-V Foundation was invited to host an all-day course and RISC-V Zone presentation at Nuremberg, Includes presentations from member companies and universities such as Andes Technology, Cloudbear, Greenwaves Technologies, Imperas Software, SiFive, Syntacore and Ultrasoc. During the exhibition, I saw many well-known embedded software and tool companies start to support RISC-V. For example, German Segger, Lauterbach, Swedish IAR, Amazon FreeRtos, embedded chip company NXP and Microchip, all show off their RISC-V MCU products.

#### RISC-V is an open source instruction set architecture

RISC-V is an open source instruction set architecture that is not a CPU product. The instruction that a CPU supports and the byte level encoding of the instruction is the CPU's Instruction Set (ISA). ISA provides an abstraction layer (interface) between CPU software and CPU hardware designers. Different CPU families, such as Intel X86, IBM/Freescale PowerPC, and ARM, have different ISA. RISC-V is the only open source ISA. It originated from the University of California, Berkeley, and uses the open source BSD license. Any enterprise, university and individual can follow the RISC-V architecture to design CPU cores.
    Commercial companies customize their own RISC-V cores, such as Western Digital's SWERV (RISCV 32IMC Core), and some commercial IP companies develop RISC-V CPU IPs. The most popular SIFive has E and S cores in series 2, 3, 5 and 7. Covering 32-64-bit embedded and high-end application processor fields.
How to manage RISC-V open source projects? The RISC-V Foundation was founded in 2015 and consists of more than 235 members, including 20 Chinese institutions. It is an open, collaborative community of software and hardware innovators, and the Foundation guides future development and promotes the widespread adoption of RISC-V ISA.
China has two alliances, the RISC-V Industry and the China Open Directive Ecology (RISC-V), to promote the development of RISC-V in China.

#### RISC-V has three major advantages

The biggest advantage of RISC-V is that it is open source and free. Free means that RISC-V allows developers to design CPUs cheaply and, if mass-produced, without having to deal with royalties. ISA open source means that developers can create their own AIOT chip architecture for specific application scenarios, such as the recently hot AIOT market. Of course, the Foundation encourages the use of RISC-V instruction set standard modules or combinations. For example, ETH Zurich's open source Zero-Riscy kernel uses RV32IMC, RV32i instructions plus M extension and C extension, where M stands for integer multiplication and division, and C for compression. NXP Vega Development Board (VGEA)MCU is Zero - RISCY open source kernel.
    RISC-V's second advantage is simplicity. With a base instruction set of just over 40, the short architecture and modular instruction set allow chip designers using RISC-V technology to develop very simple RISC-V CPUs. This CPU can consume very little power and have low code density. In order to meet the high requirements of code volume for embedded and Internet of Things, RISC-V defines an optional subset of Compressed (Compressed) instructions, represented by the letter C, or by RVC. The RV32C code is 40% smaller than the RV32 code. It performs well compared to ARM, MIPS, and x86 architectures, and is almost the same as ARM Thumb-2.
    The third advantage of RISC-V is **flexibility**. The RISC-V architecture allows users to expand the instruction set by reserving a large amount of coding space and four user instructions. This feature has gained particular attention in the current AIOT and information security markets.
    RISC-V commercial IP companies, such as Andes, also provide a Custom command tool, Andes Custom Extension, which allows users to achieve a faster and more efficient way to accelerate their applications.
    **Multi-core heterogeneity** is a feature of RISC-V architecture chip design. For example, the GAP8 CPU developed by Greenwave in France has 8 RISC-V cores and AI accelerators, low power consumption optimization, and is oriented to the devices of AI edge technology nodes.

#### Ecological construction is the key

Architecture and instruction sets are not the most important factors in determining whether a CPU will be widely used. Historically, X86 has swept desktop computers, PowerPC exclusive communication devices, ARM dominant mobile terminals, as well as 8051/PIC/MSP430/ATMEL single-chip microcomputer world, the important thing is the ecological environment owned by the CPU. For example, a general-purpose embedded CPU needs to **provide developers with easy access to Chinese documentation, easy-to-use open source business development tools, firmware libraries, software libraries, embedded OS and Linux, and rich design solutions.**
    The longest link in ecological construction is the university plan. The university plans to do a good job, students from the beginning of graduation, have mastered the CPU architecture and use methods. For example, the microcomputer principle courses in colleges and universities have been based on X86 and ARM for a long time. Embedded courses are mostly ARM architecture. In addition to ARM, there are some 8051 SCM courses.
    Today the open source RISC-V architecture is very popular in colleges and universities. On the "Salon of RISC-V Architecture Embedded Development Research and Practice Technology" organized by the Embedded System Association, Chen Yu, associate professor of Tsinghua University, pointed out that RISC-V came from the school and had been explored for a long time. Also, it's open source, and students have access to all the information about it, unlike x86 and ARM, where it's hard to get into more detail. As a result, RISC-V makes it easier to develop applications and operating systems. Many teachers choose Rust to guide students in writing a small operating system on top of RISC-V, and the more RISC-V teachers at a university focus on RISC-V or offer RISC-V based classes, the faster future graduates will pick it up. There are not many books on RISC-V in Chinese, and two books by Hu Zhenbo, founder of Xilao Technology, are valuable guides to learning about RISC-V. Recently, the Open-ISA RISC-V MCU Innovation Competition initiated by NXP is also a good attempt for the ecological construction of RISC-V. We hope to see the presence of RISC-V chips in more electronic, embedded and Internet of Things competitions.

#### Standardization or diversification?

Existing CPU architectures are mostly generic. In the IoT scenario, a lot of intelligent analytics work is moving to the margins. Customizing IoT chips using the RISC-V architecture is more flexible and tailored to specific needs. The current RISC-V architecture design, in addition to the basic instruction set to ensure the compatibility of the system software and development environment, itself allows for the expansion of new and different development applications, so as to ensure the specific requirements of IoT applications.
    NXP China MCU, senior manager of liangping recently wrote: "for this kind of non-standard parts, will be more uncomfortable beneficial rich ecological mechanism, the manufacturers to provide support and form a complete set of solutions, such as the need to modify the compiler to support the new instructions, need to change configuration debugging tools to adapt to the new bus or storage interface, etc."
The author observed that the famous Embedded compiler's recently published IAR Embedded Workbench for RISC - V can only support RV32IM/IMC/IMF/IMFC/IMFD/IMFDC basic instruction and standard extension instruction set. All kinds of customized chips can only support the tool chain maintained by the chip enterprise itself. Each chip company maintains its own compiler, SDK and tool chain of RISC-V architecture, and realizes open source based on GCC and LLVM, which is a time-consuming and labor-consuming project. We look forward to future breakthroughs in RISC-V software through collaboration between RISC-V and the Linux Foundation. However, for RISC-V to really take off on a commercial basis, it will need commercial grade tools and software.
    Internet of things and embedded will be the first to land RISC-V and the largest application market. For ecological reasons, RISC-V will evolve alongside ARM for quite some time, either in a design that can use both ARM and RISC-V, or in the same chip that can have both cores. In order to prevent the fragmentation of RISC-V, the Alliance should strengthen the guidance, first to standardize and jointly expand the RISC-V cake, and then to differentiate. The future RISC-V ecosystem will shift from chip design to developer education and practice. It is reported that at the end of this summer, a famous MCU enterprise in China will launch RISC-V universal MCU, then RISC-V "talk core" will turn to "use core", intelligent network era of embedded developers will be more convenient to evaluate and use RISC-V this new technology.

Author introduction: He Xiaoqing, vice president of Embedded System Branch of China Software Industry Association.
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