After Intel reportedly bought the industry-leading RISC-V design company SiFive for US $2 billion, the open source RISC-V instruction set architecture is gaining more mainstream attention. Unfortunately, RISC-V has long been downgraded to smaller chips and microcontrollers, limiting its appeal. However, with RISC-V International, the organization responsible for the development of RISC-V instruction set architecture (ISA), announcing plans to extend the architecture to high-performance computing, artificial intelligence and supercomputing applications, this situation should change soon.

RISC-V open source ISA was first launched in 2016, but the first core is only applicable to microcontroller and some basic system-on-chip designs. However, after several years of development, many chip developers (such as Alibaba) have created designs for cloud data centers, AI workloads (such as Tensorrent led by Jim Keller) and advanced storage applications (such as Seagate and Western Data).

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This means that developers are very interested in high-performance RISC-V chips. However, in order to promote the adoption of RISC-V ISA by edge computing, high-performance computing and supercomputing applications, the industry needs a stronger hardware and software ecosystem (as well as compatibility with legacy applications and benchmarks). This is where RISC-V SIG for HPC works.

At present, RISC-V SIG-HPC has 141 members in its mailing list, as well as 10 active members from research, academia and chip industry. The key task of the growing SIG is to put forward various new HPC-specific instructions and extensions, and combine with other technologies to ensure that HPC requirements are considered for the evolving ISA. As part of this task, SIG needs to define AI/HPC/edge requirements and draw a feature and function path to achieve the degree that RISC-V competes with ARM, x86 and other architectures.

RISC-V SIG-HPC also has short-term goals. In 2021, the group will focus on HPC software ecosystem. First, the team plans to find RISC-V ISA open-source software (benchmarks, libraries and actual programs) that can be used out of the box. This process is set to automation. The first survey will focus on applications such as GROMACS, Quantum ESPRESSO and CP2K; FFT, BLAS, GCC, LLVM and other libraries; And benchmarks such as HPL and HPCG.

RISC-V SIG-HPC will develop a more detailed road map after the ecosystem is solidified. The long-term goal of RISC-V SIG is to establish an open source ecosystem of hardware and software to solve the emerging applications with high performance requirements, while meeting the legacy requirements.

How many years will it take? Only time will prove everything, but industry support from Intel and other large companies will certainly help speed up this schedule.

Source: 锋哥爱学习 2023-02-14 For academic sharing only, please indicate the source for reprinting. In case of infringement, please contact email:lvzhiqiang@perfxlab.com Delete or modify!